The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for reading, controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.
One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662, incorporated herein by reference). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to FIGS. 1A, 1B and 1C, in one exemplary embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The gate 16 is disposed on a dielectric material above body region 18. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 30 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, a logic high or State “1” corresponds to an increased concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or State “1”.
Conventional reading is performed by applying a small drain bias and a gate bias above the transistor threshold voltage. The sensed drain current is determined by the charge stored in the floating body giving a possibility to distinguish between the states “1” and “0”. A floating body memory device has two different current states corresponding to the two different logical states: “1” and “0”.
In one conventional technique, the memory cell is read by applying a small bias to the drain of the transistor as well as a gate bias which is above the threshold voltage of the transistor. In this regard, in the context of memory cells employing N-type transistors, a positive voltage is applied to one or more word lines 28 to enable the reading of the memory cells associated with such word lines. The amount of drain current is determined/affected by the charge stored in the electrically floating body region of the transistor. As such, conventional reading techniques sense the amount of the channel current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell to determine the state of the memory cell; a floating body memory cell may have two or more different current states corresponding to two or more different logical states (for example, two different current conditions/states corresponding to the two different logical states: “1” and “0”).
In short, conventional writing programming techniques for memory cells having an N-channel type transistor often provide an excess of majority carriers by channel impact ionization (see, FIG. 3A) or by band-to-band tunneling (gate-induced drain leakage “GIDL”) (see, FIG. 3B). The majority carrier may be removed via drain side hole removal (see, FIG. 4A), source side hole removal (see, FIG. 4B), or drain and source hole removal, for example, using the back gate pulsing (see, FIG. 4C).
The memory cell 12 having electrically floating body transistor 14 may be programmed/read using other techniques including techniques that may, for example, provide lower power consumption relative to conventional techniques. For example, memory cell 12 may be programmed, read and/or controlled using the techniques and circuitry described and illustrated in U.S. Non-Provisional patent application Ser. No. 11/509,188, filed on Aug. 24, 2006, and entitled “Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same” (hereinafter “the '188 application”), which is incorporated by reference herein. In one aspect, the '188 application is directed to programming, reading and/or control methods which allow low power memory programming and provide larger memory programming window (both relative to at least the conventional programming techniques).
With reference to FIG. 5, in one exemplary embodiment, the '188 application employs, writes or programs a logic “1” or logic high using control signals (having predetermined voltages, for example, Vg=0v, Vs=0v, and Vd=2.5v) which are applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12. Such control signals induce or cause impact ionization and/or the avalanche multiplication phenomenon (FIG. 5). The predetermined voltages of the control signals, in contrast to the conventional method program or write logic “1” in the transistor of the memory cell via impact ionization and/or avalanche multiplication in the electrically floating body. In one embodiment, it is preferred that the bipolar transistor current responsible for impact ionization and/or avalanche multiplication in the floating body is initiated and/or induced by a control pulse which is applied to gate 16. Such a pulse may induce the channel impact ionization which increases the floating body potential and turns on the bipolar current. An advantage of the described method is that larger amount of the excess majority carriers is generated compared to other techniques.
Further, with reference to FIG. 6, when writing or programming logic “0” in transistor 14 of memory cell 12, in one embodiment of the '188 application, the control signals (having predetermined voltages (for example, Vg=1.5v, Vs=0v and Vd=0v) are different and, in at least one embodiment, higher than a holding voltage (if applicable)) are applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12. Such control signals induce or provide removal of majority carriers from the electrically floating body of transistor 14. In one embodiment, the majority carriers are removed, eliminated or ejected from body region 18 through source region 20 and drain region 22. (See, FIG. 6). In this embodiment, writing or programming memory cell 12 with logic “0” may again consume lower power relative to conventional techniques.
When memory cell 12 is implemented in a memory cell array configuration, it may be advantageous to implement a “holding” operation for certain memory cells 12 when programming one or more other memory cells 12 of the memory cell array to enhance the data retention characteristics of such certain memory cells 12. The transistor 14 of memory cell 12 may be placed in a “holding” state via application of control signals (having predetermined voltages) that are applied to gate 16 and source region 20 and drain region 22 of transistor 14 of memory cell 12. In combination, such control signals provide, cause and/or induce majority carrier accumulation in an area that is close to the interface between gate dielectric 32 and electrically floating body region 18. (See, FIG. 7). In this embodiment, it may be preferable to apply a negative voltage to gate 16 where transistor 14 is an N-channel type transistor.
With reference to FIG. 8, in one embodiment of the '188 application, the data state of memory cell 12 may be read and/or determined by applying control signals (having predetermined voltages, for example, Vg=−0.5v, Vs=2.5v and Vd=0v) to gate 16 and source region 20 and drain region 22 of transistor 14. Such signals, in combination, induce and/or cause the bipolar transistor current in those memory cells 12 storing a logic state “1”. For those memory cells that are programmed to a logic state “0”, such control signals do not induce and/or cause a considerable, substantial or sufficiently measurable bipolar transistor current in the cells programmed to “0” state. (See, the '188 application, which, as noted above, is incorporated by reference).
As mentioned above, the reading may be performed using positive voltages applied to word lines 28. As such, transistors 14 of device 10 are periodically pulsed between a positive gate bias, which (1) drives majority carriers (holes for N-channel transistors) away from the interface between gate insulator 32 and body region 18 of transistor 14 and (2) causes minority carriers (electrons for N-channel transistors) to flow from source region 20 and drain region 22 into a channel formed below gate 16, and the negative gate bias, which causes majority carriers (holes for N-channel transistors) to accumulate in or near the interface between gate 16 and body region 18 of transistor 14.
Notably, conventional programming techniques may employ relatively high drain and/or gate bias voltages, which may increase the power consumption of the memory cell. Moreover, relatively high bias voltages may present device scaling challenges due to the reduction in device features. The proposed memory cell does not require any high voltages and provides a low power and scalable memory.